HCPL-4506 A4506 HP4506 IC OPTO ISOLATE

HCPL-4506 A4506 HP4506 IC OPTO ISOLATE

DATA SHEET https://pdf1.alldatasheet.com/datasheet-pdf/view/64636/HP/HCPL-4506.html

1-49

H

Intelligent Power Module and

Gate Drive Interface Optocouplers

Technical Data

Features

• Performance Specified for

Common IPM Applications

over Industrial Temperature

Range: -40°C to 100°C

• Fast Maximum Propagation

Delays

tPHL = 400 ns

tPLH = 550 ns

• Minimized Pulse Width

Distortion (PWD = 450 ns)

• 15 kV/ms Minimum Common

Mode Transient Immunity at

VCM = 1500 V

• CTR > 44% at IF = 10 mA

• Safety Approval

UL Recognized - 2500 V rms

for 1 minute (5000 V rms for

1 minute for HCNW4506 and

HCPL-4506 Option 020) per

UL1577

CSA Approved

VDE 0884 Approved

-VIORM = 630 V peak for

HCPL-4506 Option 060

-VIORM = 1414 V peak for

HCNW4506

BSI Certified (HCNW4506)

Applications

• IPM Isolation

• Isolated IGBT/MOSFET Gate

Drive

• AC and Brushless DC Motor

Drives

• Industrial Inverters

Description

The HCPL-4506 and HCPL-0466

contain a GaAsP LED while the

HCNW4506 contains an AlGaAs

LED. The LED is optically

coupled to an integrated high gain

photo detector. Minimized propa-

The connection of a 0.1 mF bypass capacitor between pins 5 and 8 is recommended.

gation delay difference between

devices make these optocouplers

excellent solutions for improving

inverter efficiency through

reduced switching dead time.

An on chip 20 kW output pull-up

resistor can be enabled by shorting

output pins 6 and 7, thus

eliminating the need for an

external pull-up resistor in

common IPM applications. Specifications

and performance plots

are given for typical IPM

applications.

HCPL-4506

HCPL-0466

HCNW4506

Functional Diagram Truth Table

LED VO

ON L

OFF H

8

7

6

1

3

SHIELD

5

2

4

20 kW

NC

ANODE

CATHODE

NC

VCC

VL

VO

GND

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to

prevent damage and/or degradation which may be induced by ESD.

Selection Guide

Operating Temperature

TA [°C] Single Channel Packages

8-Pin DIP Small Outline Widebody

Min. Max. (300 Mil) SO-8 (400 Mil) Hermetic*

-40 100 HCPL-4506 HCPL-0466 HCNW4506

-55 125 HCPL-5300

HCPL-5301

*Technical data for these products are on separate HP publications.

5965-3603E

1-50

0.635 ± 0.25

(0.025 ± 0.010)

12° NOM.

9.65 ± 0.25

(0.380 ± 0.010)

0.635 ± 0.130

(0.025 ± 0.005)

7.62 ± 0.25

(0.300 ± 0.010)

8 7 6 5

1 2 3 4

9.65 ± 0.25

(0.380 ± 0.010)

6.350 ± 0.25

(0.250 ± 0.010)

1.016 (0.040)

1.194 (0.047)

1.194 (0.047)

1.778 (0.070)

9.398 (0.370)

9.906 (0.390)

4.826

(0.190)TYP.

0.381 (0.015)

0.635 (0.025)

PAD LOCATION (FOR REFERENCE ONLY)

1.080 ± 0.320

(0.043 ± 0.013)

4.19

(0.165)

MAX.

1.780

(0.070)

MAX.

1.19

(0.047)

MAX.

2.54

(0.100)

BSC

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

0.254 + 0.076

- 0.051

(0.010 + 0.003)

- 0.002)

9.65 ± 0.25

(0.380 ± 0.010)

1.78 (0.070) MAX.

1.19 (0.047) MAX.

HP XXXXZ

YYWW

DATE CODE

1.080 ± 0.320

(0.043 ± 0.013)

2.54 ± 0.25

(0.100 ± 0.010)

0.51 (0.020) MIN.

0.65 (0.025) MAX.

4.70 (0.185) MAX.

2.92 (0.115) MIN.

DIMENSIONS IN MILLIMETERS AND (INCHES).

8 7 6 5

1 2 3 4

5° TYP.

OPTION CODE*

UL

RECOGNITION

UR

0.254 + 0.076

- 0.051

(0.010 + 0.003)

- 0.002)

7.62 ± 0.25

(0.300 ± 0.010)

TYPE NUMBER

* MARKING CODE LETTER FOR OPTION NUMBERS.

"L" = OPTION 020

"V" = OPTION 060

OPTION NUMBERS 300 AND 500 NOT MARKED.

6.35 ± 0.25

(0.250 ± 0.010)

Package Outline Drawings

Figure 2. HCPL-4506 Gull Wing Surface Mount Option #300 Outline Drawing.

Figure 1. HCPL-4506 Outline Drawing (Standard DIP Package).

Ordering Information

Specify Part Number followed by Option Number (if desired).

Example:

HCPL-4506#XXX

020 = UL 5000 V rms/1 Minute Option*

060 = VDE 0884 VIORM = 630 V peak Option*

300 = Gull Wing Surface Mount Option†

500 = Tape and Reel Packaging Option

Option data sheets are available. Contact your Hewlett-Packard sales representative or authorized

distributor for information.

*For HCPL-4506 only. Combination of Option 020 and

Option 060 is not available.

†Gull wing surface mount option applies to through

hole parts only.

1-51

1.00 ± 0.15

(0.039 ± 0.006)

7° NOM.

12.30 ± 0.30

(0.484 ± 0.012)

0.75 ± 0.25

(0.030 ± 0.010)

11.00

(0.433)

8 7 6 5

1 2 3 4

11.15 ± 0.15

(0.442 ± 0.006)

9.00 ± 0.15

(0.354 ± 0.006)

1.3

(0.051)

12.30 ± 0.30

(0.484 ± 0.012)

6.15

(0.242)TYP.

0.9

(0.035)

PAD LOCATION (FOR REFERENCE ONLY)

1.78 ± 0.15

(0.070 ± 0.006)

4.00

(0.158)

MAX.

1.55

(0.061)

MAX.

2.54

(0.100)

BSC

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

0.254 + 0.076

- 0.0051

(0.010+ 0.003)

- 0.002)

MAX.

8 7 6 5

1 2 3 4

11.15 ± 0.15

(0.442 ± 0.006)

1.78 ± 0.15

(0.070 ± 0.006)

5.10

(0.201)

MAX.

1.55

(0.061)

MAX.

2.54 (0.100)

TYP.

DIMENSIONS IN MILLIMETERS (INCHES).

7° TYP.

0.254 + 0.076

- 0.0051

(0.010+ 0.003)

- 0.002)

11.00

(0.433)

9.00 ± 0.15

(0.354 ± 0.006)

MAX.

10.16 (0.400)

TYP.

HP

HCNWXXXX

YYWW

DATE CODE

TYPE NUMBER

0.51 (0.021) MIN.

0.40 (0.016)

0.56 (0.022)

3.10 (0.122)

3.90 (0.154)

XXX

YWW

8 7 6 5

1 2 3 4

5.842 ± 0.203

(0.236 ± 0.008)

3.937 ± 0.127

(0.155 ± 0.005)

0.381 ± 0.076

(0.016 ± 0.003) 1.270

(0.050)

BSG

5.080 ± 0.127

(0.200 ± 0.005)

3.175 ± 0.127

(0.125 ± 0.005) 1.524

(0.060)

45° X 0.432

(0.017)

0.228 ± 0.025

(0.009 ± 0.001)

TYPE NUMBER

(LAST 3 DIGITS)

DATE CODE

0.305

(0.012)

DIMENSIONS IN MILLIMETERS (INCHES). MIN.

LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

0.152 ± 0.051

(0.006 ± 0.002)

7°

Figure 3. HCPL-0466 Outline Drawing (8-Pin Small Outline Package).

Figure 4a. HCNW4506 Outline Drawing (8-Pin Widebody Package).

Pin Location (for reference only)

Figure 4b. HCNW4506 Outline Drawing (8-Pin Widebody Package with Gull Wing Surface Mount Option 300).

1-52

Insulation and Safety Related Specifications

8-Pin DIP Widebody

(300 Mil) SO-8 (400 Mil)

Parameter Symbol Value Value Value Units Conditions

Minimum External L(101) 7.1 4.9 9.6 mm Measured from input terminals

Air Gap (External to output terminals, shortest

Clearance) distance through air.

Minimum External L(102) 7.4 4.8 10.0 mm Measured from input terminals

Tracking (External to output terminals, shortest

Creepage) distance path along body.

Minimum Internal 0.08 0.08 1.0 mm Through insulation distance,

Plastic Gap conductor to conductor, usually

(Internal Clearance) the direct distance between the

photoemitter and photodetector

inside the optocoupler cavity.

Minimum Internal NA NA 4.0 mm Measured from input terminals

Tracking (Internal to output terminals, along

Creepage) internal cavity.

Tracking Resistance CTI 200 200 200 Volts DIN IEC 112/VDE 0303 Part 1

(Comparative

Tracking Index)

Isolation Group IIIa IIIa IIIa Material Group

(DIN VDE 0110, 1/89, Table 1)

Option 300 - surface mount classification is Class A in accordance with CECC 00802.

Regulatory Information

The devices contained in this data

sheet have been approved by the

following organizations:

UL

Recognized under UL 1577,

Component Recognition

Program, File E55361.

CSA

Approved under CSA Component

Acceptance Notice #5, File CA

88324.

VDE

Approved according to VDE

0884/06.92 (HCNW4506 and

HCPL-4506 Option 060 only).

BSI

Certification according to

BS451:1994

(BS EN60065:1994);

BS EN60950:1992

(BS7002:1992) and

EN41003:1993 for Class II

applications (HCNW4506 only).

Note: Use of nonchlorine activated fluxes is recommended.

240

DT = 115°C, 0.3°C/SEC

0

DT = 100°C, 1.5°C/SEC

DT = 145°C, 1°C/SEC

TIME – MINUTES

TEMPERATURE – °C

220

200

180

160

140

120

100

80

60

40

20

0

260

1 2 3 4 5 6 7 8 9 10 11 12

Solder Reflow Temperature Profile

1-53

VDE 0884 Insulation Related Characteristics

(HCPL-4506 OPTION 060 ONLY)

Description Symbol Characteristic Units

Installation classification per DIN VDE 0110/1.89, Table 1

for rated mains voltage £ 300 V rms I-IV

for rated mains voltage £ 450 V rms I-III

Climatic Classification 55/100/21

Pollution Degree (DIN VDE 0110/1.89) 2

Maximum Working Insulation Voltage VIORM 630 V peak

Input to Output Test Voltage, Method b*

VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, VPR 1181 V peak

Partial Discharge < 5 pC

Input to Output Test Voltage, Method a*

VIORM x 1.5 = VPR, Type and sample test, VPR 945 V peak

tm = 60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage*

(Transient Overvoltage, tini = 10 sec) VIOTM 6000 V peak

Safety Limiting Values

(Maximum values allowed in the event of a failure,

also see Figure 18, Thermal Derating curve.)

Case Temperature TS 175 °C

Input Current IS,INPUT 230 mA

Output Power PS,OUTPUT 600 mW

Insulation Resistance at TS, VIO = 500 V RS ³ 109 W

VDE 0884 Insulation Related Characteristics (HCNW4506 ONLY)

Description Symbol Characteristic Units

Installation classification per DIN VDE 0110/1.89, Table 1

for rated mains voltage £ 600 V rms I-IV

for rated mains voltage £ 1000 V rms I-III

Climatic Classification 55/100/21

Pollution Degree (DIN VDE 0110/1.89) 2

Maximum Working Insulation Voltage VIORM 1414 V peak

Input to Output Test Voltage, Method b*

VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, VPR 2652 V peak

Partial Discharge < 5 pC

Input to Output Test Voltage, Method a*

VIORM x 1.5 = VPR, Type and sample test, VPR 2121 V peak

tm = 60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage*

(Transient Overvoltage, tini = 10 sec) VIOTM 8000 V peak

Safety Limiting Values

(Maximum values allowed in the event of a failure,

also see Figure 18, Thermal Derating curve.)

Case Temperature TS 150 °C

Input Current IS,INPUT 400 mA

Output Power PS,OUTPUT 700 mW

Insulation Resistance at TS, VIO = 500 V RS ³ 109 W

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a

detailed description.

Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in

application.

1-54

Electrical Specifications

Over recommended operating conditions unless otherwise specified:

TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†

Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note

Current Transfer Ratio CTR 44 90 % IF = 10 mA, VO = 0.6 V 5

Low Level Output Current IOL 4.4 9.0 mA IF = 10 mA, VO = 0.6 V 5,6

Low Level Output Voltage VOL 0.3 0.6 V IO = 2.4 mA

Input Threshold Current ITH 1.5 5.0 mA VO = 0.8 V, IO = 0.75 mA 5 14

High Level Output Current IOH 5 50 mA VF = 0.8 V 7

High Level Supply Current ICCH 0.6 1.3 mA VF = 0.8 V, VO = Open 14

Low Level Supply Current ICCL 0.6 1.3 mA IF = 10 mA, VO = Open 14

Input Forward Voltage VF 1.5 1.8 V HCPL-4506 IF = 10 mA 8

HCPL-0466

1.6 1.85 HCNW4506 9

Temperature Coefficient DVF /DTA -1.6 mV/°C HCPL-4506 IF = 10 mA

of Forward Voltage HCPL-0466

-1.3 HCNW4506

Input Reverse Breakdown BVR 5 V HCPL-4506 IR = 100 mA

Voltage HCPL-0466

3 HCNW4506

Input Capacitance CIN 60 pF HCPL-4506 f = 1 MHz,

HCPL-0466 VF = 0 V

72 HCNW4506

Internal Pull-up Resistor RL 14 20 25 kW TA = 25°C 10,11

Internal Pull-up Resistor DRL/DTA 0.014 kW/°C

Temperature Coefficient

*All typical values at 25°C, VCC = 15 V.

†VF(off) = -3 V to 0.8 V for HCNW4506.

Recommended Operating Conditions

Parameter Symbol Min. Max. Units

Power Supply Voltage VCC 4.5 30 Volts

Output Voltage VO 0 30 Volts

Input Current (ON) IF(on) 10 20 mA

Input Voltage (OFF) VF(off)* -5 0.8 V

Operating Temperature TA -40 100 °C

*Recommended VF(OFF) = -3 V to 0.8 V for HCNW4506.

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units

Storage Temperature TS -55 125 °C

Operating Temperature TA -40 100 °C

Average Input Current[1] IF(avg) 25 mA

Peak Input Current[2] (50% duty cycle, £ 1 ms pulse width) IF(peak) 50 mA

Peak Transient Input Current (<1 ms pulse width, 300 pps) IF(tran) 1.0 A

Reverse Input Voltage (Pin 3-2) HCPL-4506, HCPL-0466 VR 5 Volts

HCNW4506 3

Average Output Current (Pin 6) IO(avg) 15 mA

Resistor Voltage (Pin 7) V7 -0.5 VCC Volts

Output Voltage (Pin 6-5) VO -0.5 30 Volts

Supply Voltage (Pin 8-5) VCC -0.5 30 Volts

Output Power Dissipation[3] PO 100 mW

Total Power Dissipation[4] PT 145 mW

Lead Solder Temperature (HCPL-4506) 260°C for 10 s, 1.6 mm below seating plane

Lead Solder Temperature (HCNW4506) 260°C for 10 s (up to seating plane)

Infrared and Vapor Phase Reflow Temperature See Package Outline Drawings Section

(HCPL-0466 and Option 300)

1-55

Switching Specifications (RL= 20 kW External)

Over recommended operating conditions unless otherwise specified:

TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†

Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note

Propagation Delay tPHL IF(on) = 10 mA, 10, 9,

Time to Low VF(off) = 0.8 V, 12, 12,

Output Level 14-17 14

Propagation Delay tPLH

Time to High

Output Level

Pulse Width PWD 200 450 ns CL = 100 pF 18

Distortion

Propagation Delay tPLH-tPHL -150 200 450 ns 15

Difference Between

Any 2 Parts

Output High Level |CMH| 15 30 kV/ms IF = 0 mA, VCC = 15.0 V, 11 16

Common Mode VO > 3.0 V CL = 100 pF,

Transient Immunity VCM = 1500 VP-P

Output Low Level |CML| 15 30 kV/ms IF = 10 mA 17

Common Mode VO < 1.0 V

Transient Immunity

Switching Specifications (RL = Internal Pull-up)

Over recommended operating conditions unless otherwise specified:

TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†

Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note

Propagation Delay tPHL 20 200 400 ns IF(on) = 10 mA, VF(off) = 0.8 V, 10, 9-12,

Time to Low VCC = 15.0 V, CL = 100 pF, 13 14

Output Level VTHLH = 2.0 V, VTHHL = 1.5 V

Propagation Delay tPLH 220 450 650 ns

Time to High

Output Level

Pulse Width PWD 250 500 ns 18

Distortion

Propagation Delay tPLH-tPHL -150 250 500 ns 15

Difference Between

Any 2 Parts

Output High Level |CMH| 30 kV/ms IF = 0 mA, VCC = 15.0 V, 11 16

Common Mode VO > 3.0 V CL = 100 pF,

Transient Immunity VCM = 1500 VP-P,

Output Low Level |CML| 30 kV/ms IF = 16 mA, 17

Common Mode VO < 1.0 V

Transient Immunity

Power Supply PSR 1.0 VP-P Square Wave, tRISE, tFALL 14

Rejection > 5 ns, no bypass capacitors

*All typical values at 25°C, VCC = 15 V.

†VF(off) = -3 V to 0.8 V for HCNW4506.

VCC = 15.0 V,

VTHLH = 2.0 V,

VTHHL = 1.5 V

130 CL = 10 pF

30 200 400 ns CL = 100 pF

100 ns CL = 10 pF

270 400 550 ns CL = 100 pF

TA = 25°C

TA = 25°C

1-56

Package Characteristics

Over recommended temperature (TA = -40°C to 100°C) unless otherwise specified.

Parameter Sym. Min. Typ.* Max. Units Test Conditions Fig. Note

Input-Output Momentary VISO 2500 V rms HCPL-4506 RH < 50%, 6, 7, 8

Withstand Voltage† HCPL-0466 t = 1 min.

5000 HCNW4506 6, 8, 13

Option 020

5000 HCNW4506 6, 8

Resistance RI-O 1012 W HCPL-4506 VI-O = 500 Vdc 6

(Input-Output) HCPL-0466

1012 1013 HCNW4506

Capacitance CI-O 0.6 pF HCPL-4506 f = 1 MHz 6

(Input-Output) HCPL-0466

0.5 HCNW4506

*All typical values at 25°C, VCC = 15 V.

†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output

continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if

applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance

Voltage,” publication number 5963-2203E.

Notes:

1. Derate linearly above 90°C free-air

temperature at a rate of 0.8 mA/°C.

2. Derate linearly above 90°C free-air

temperature at a rate of 1.6 mA/°C.

3. Derate linearly above 90°C free-air

temperature at a rate of 3.0 mW/°C.

4. Derate linearly above 90°C free-air

temperature at a rate of 4.2 mW/°C.

5. CURRENT TRANSFER RATIO in

percent is defined as the ratio of

output collector current (IO) to the

forward LED input current (IF) times

100.

6. Device considered a two-terminal

device: Pins 1, 2, 3, and 4 shorted

together and Pins 5, 6, 7, and 8

shorted together.

7. In accordance with UL 1577, each

optocoupler is proof tested by

applying an insulation test voltage

³ 3000 V rms for 1 second (leakage

detection current limit, II-O £ 5 mA).

This test is performed before the

100% Production test shown in the

VDE 0884 Insulation Related

Characteristics Table, if applicable.

8. For option 020, in accordance with

UL 1577, each optocoupler is proof

tested by applying an insulation test

voltage ³ 6000 V rms for 1 second

(leakage detection current limit, II-O

£ 5 mA). This test is performed before

the 100% Production test for partial

discharge (method b) shown in the

VDE 0884 Insulation Related

Characteristics Table, if applicable.

9. Pulse: f = 20 kHz, Duty Cycle = 10%.

10. The internal 20 kW resistor can be

used by shorting pins 6 and 7

together.

11. Due to tolerance of the internal

resistor, and since propagation delay

is dependent on the load resistor

value, performance can be improved

by using an external 20 kW 1% load

resistor. For more information on

how propagation delay varies with

load resistance, see Figure 12.

12. The RL = 20 kW, CL = 100 pF load

represents a typical IPM (Intelligent

Power Module) load.

13. See Option 020 data sheet for more

information.

14. Use of a 0.1 mF bypass capacitor

connected between pins 5 and 8 can

improve performance by filtering

power supply line noise.

15. The difference between tPLH and tPHL

between any two devices under the

same test condition. (See IPM Dead

Time and Propagation Delay

Specifications section.)

16. Common mode transient immunity in

a Logic High level is the maximum

tolerable dVCM/dt of the common

mode pulse, VCM, to assure that the

output will remain in a Logic High

state (i.e., VO > 3.0 V).

17. Common mode transient immunity in

a Logic Low level is the maximum

tolerable dVCM/dt of the common

mode pulse, VCM, to assure that the

output will remain in a Logic Low

state (i.e., VO < 1.0 V).

18. Pulse Width Distortion (PWD) is

defined as |tPHL - tPLH| for any given

device.

TA = 25°C

1-57

Figure 8. HCPL-4506 and HCPL-0466

Input Current vs. Forward Voltage.

Figure 9. HCNW4506 Input Current

vs. Forward Voltage.

Figure 6. Normalized Output Current

vs. Temperature.

Figure 5. Typical Transfer

Characteristics.

Figure 7. High Level Output

Current vs. Temperature.

Figure 10. Propagation Delay Test Circuit.

IO – OUTPUT CURRENT – mA

0

IF – FORWARD LED CURRENT – mA

6

4

2

5

10

10 15 20

VO = 0.6 V

8

0

100 °C

25 °C

-40 °C

NORMALIZED OUTPUT CURRENT

TA – TEMPERATURE – °C

0.95

0.90

0.85

0 40 60 100

IF = 10 mA

VO = 0.6 V

1.00

-40 -20 20 80

1.05

0.80

IF – FORWARD CURRENT – mA

1.10

0.001

VF – FORWARD VOLTAGE – VOLTS

1.60

10

1.0

0.1

1.20

1000

1.30 1.40 1.50

TA = 25°C

IF

VF

+

–

0.01

100

0.1 μF

VCC = 15 V

I 20 kW F(ON) =10 mA

VOUT

CL*

+–

*TOTAL LOAD CAPACITANCE

+

–

If

VO

VTHHL

tPHL tPLH

tf tr

90%

10%

90%

10%

VTHLH

8

7

6

1

3

SHIELD

5

2

4

5 V

20 kW

IF – INPUT FORWARD CURRENT – mA

0.001

VF – INPUT FORWARD VOLTAGE – V

1

0.1

0.01

1.0

100

1.4 1.8 2.0

TA = 25 °C

10

0.8 1.2 1.6

IF

VF

+

–

IOH – HIGH LEVEL OUTPUT CURRENT – μA

TA – TEMPERATURE – °C

15.0

10.0

5.0

0 40 60 100

20.0

-40 -20 20 80

0

4.5 V

30 V

VF = 0.8 V

VCC = VO = 4.5 V OR 30 V

1-58

Figure 12. Propagation Delay with

External 20 kW RL vs. Temperature.

Figure 13. Propagation Delay with

Internal 20 kW RL vs. Temperature.

Figure 14. Propagation Delay vs. Load

Resistance.

Figure 11. CMR Test Circuit. Typical CMR Waveform.

Figure 17. Propagation Delay vs. Input

Current.

Figure 15. Propagation Delay vs. Load

Capacitance.

Figure 16. Propagation Delay vs.

Supply Voltage.

0.1 μF

VCC = 15 V

20 kW

A

IF

VOUT

100 pF*

+–

*100 pF TOTAL

CAPACITANCE

+

–

+–

B

VFF

VCM = 1500 V

8

7

6

1

3

SHIELD

5

2

4

20 kW

VCM

Dt

OV

VO

VO

SWITCH AT A: IF = 0 mA

SWITCH AT B: IF = 10 mA

VCC

VOL

VCM

Dt

dV

dt

=

tP – PROPAGATION DELAY – ns

TA – TEMPERATURE – °C

400

300

200

0 40 60 100

500

-40 -20 20 80

tPLH

tPHL

IF = 10 mA

VCC = 15 V

CL = 100 pF

RL = 20 kW (EXTERNAL)

100

tP – PROPAGATION DELAY – ns

RL – LOAD RESISTANCE – K W

600

400

200

30 50

800

0 10 20 40

tPLH

tPHL

IF = 10 mA

VCC = 15 V

CL = 100 pF

TA = 25 °C

tP – PROPAGATION DELAY – ns

0

CL – LOAD CAPACITANCE – pF

800

600

400

100

1400

200 300 400

IF = 10 mA

VCC = 15 V

RL = 20 kW

TA = 25°C

200

1000 tPLH

tPHL

1200

0 500

tP – PROPAGATION DELAY – ns

0

VCC – SUPPLY VOLTAGE – V

800

600

400

10

1400

15 20 25

IF = 10 mA

CL = 100 pF

RL = 20 kW

TA = 25°C

200

1000 tPLH

tPHL

5 30

1200

tP – PROPAGATION DELAY – ns

100

IF – FORWARD LED CURRENT – mA

300

10

500

15

VCC = 15 V

CL = 100 pF

RL = 20 kW

TA = 25°C

200

400

tPLH

tPHL

0 5 20

tP – PROPAGATION DELAY – ns

TA – TEMPERATURE – °C

400

300

200

0 40 60 100

500

-40 -20 20 80

tPLH

tPHL

IF = 10 mA

VCC = 15 V

CL = 100 pF

RL = 20 kW

(INTERNAL)

100

1-59

Figure 20. Optocoupler Input to

Output Capacitance Model for

Unshielded Optocouplers.

Figure 19. Recommended LED Drive Circuit.

Figure 18. Thermal Derating Curve, Dependence of Safety Limiting Value with

Case Temperature per VDE 0884.

Figure 22. LED Drive Circuit with Resistor Connected to LED

Anode (Not Recommended).

Figure 21. Optocoupler Input to

Output Capacitance Model for

Shielded Optocouplers.

0.1 μF

VCC = 15 V

20 kW

CMOS

310 W

+5 V

VOUT

100 pF

+–

*100 pF TOTAL

CAPACITANCE

8

7

6

1

3

SHIELD

5

2

4

20 kW

8

7

6

1

3

SHIELD

5

2

4

CLEDP

CLEDN

20 kW

8

7

6

1

3

SHIELD

5

2

4

CLEDP

CLEDN

CLED01

CLED02

20 kW

0.1 μF

VCC = 15 V

20 kW

CMOS

310 W

+5 V

VOUT

100 pF

+–

*100 pF TOTAL

CAPACITANCE

8

7

6

1

3

SHIELD

5

2

4

20 kW

OUTPUT POWER – PS, INPUT CURRENT – IS

0

0

TS – CASE TEMPERATURE – °C

175

1000

50

400

25 75 100 125 150

600

800

200

100

300

500

700

900

PS (mW)

IS (mA)

HCNW4506

OUTPUT POWER – PS, INPUT CURRENT – IS

0

0

TS – CASE TEMPERATURE – °C

50 200

400

25 75 100 125 150

600

800

200

100

300

500

700

PS (mW)

IS (mA)

HCPL-4506 OPTION 060

175

(230)

Figure 23. AC Equivalent Circuit for Figure 22 During

Common Mode Transients.

20 kW

* THE ARROWS INDICATE THE DIRECTION OF CURRENT

FLOW FOR +dVCM/dt TRANSIENTS.

310 W

VOUT

100 pF

+–

ITOTAL*

VCM

8

7

6

1

3

SHIELD

5

2

4

20

kW

CLEDN

CLED01

CLED02

ICLEDP

IF CLEDP

ICLED01

1-60

Figure 27. Recommended LED Drive

Circuit for Ultra High CMR.

Figure 24. AC Equivalent Circuit for Figure 19 During

Common Mode Transients.

Figure 25. Not Recommended Open

Collector LED Drive Circuit.

Figure 26. AC Equivalent Circuit for Figure 25 During

Common Mode Transients.

Q1

+5 V

8

7

6

1

3

SHIELD

5

2

4

20 kW

20 kW

* THE ARROWS INDICATE THE DIRECTION OF CURRENT

FLOW FOR +dVCM/dt TRANSIENTS.

VOUT

100 pF

+–

VCM

8

7

6

1

3

SHIELD

5

2

4

20

C kW LEDP

CLEDN

CLED01

CLED02

ICLEDN*

Q1

+5 V

8

7

6

1

3

SHIELD

5

2

4

20 kW

20 kW

* THE ARROWS INDICATE THE DIRECTION OF CURRENT

FLOW FOR +dVCM/dt TRANSIENTS.

** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH

PERFORMANCE. VR < VF (OFF) DURING +dVCM/dt.

VOUT

100 pF

+–

VCM

8

7

6

1

3

SHIELD

5

2

4

20

C kW LEDP

CLEDN

CLED01

CLED02

ICLEDN*

310 W

+ VR** –

Figure 28. Typical Application Circuit.

0.1 μF

20 kW

CMOS

310 W

+5 V

VOUT1

ILED1

VCC1

M

HCPL-4506

HCPL-4506

HCPL-4506

HCPL-4506

HCPL-4506

Q2

Q1

-HV

+HV

IPM

8

7

6

1

3

SHIELD

5

2

4

20 kW

HCPL-4506

0.1 μF

20 kW

CMOS

310 W

+5 V

VOUT2

ILED2

8 VCC2

7

6

1

3

SHIELD

5

2

4

20 kW

HCPL-4506

1-61

Figure 30. Waveforms for Dead Time Calculation.

Figure 29. Minimum LED Skew for Zero Dead Time.

VOUT1

VOUT2

ILED2

tPLH MAX.

PDD* MAX. =

(tPLH-tPHL) MAX. = tPLH MAX. - tPHL MIN.

tPHL

MIN.

ILED1

Q1 ON

Q2 OFF

Q1 OFF

Q2 ON

*PDD = PROPAGATION DELAY DIFFERENCE

NOTE: THE PROPAGATION DELAYS USED TO CALCULATE

PDD ARE TAKEN AT EQUAL TEMPERATURES.

VOUT1

VOUT2

ILED2

tPLH

MIN.

MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)

= (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.)

= (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.)

= PDD* MAX. - PDD* MIN.

tPHL

MIN.

ILED1

Q1 ON

Q2 OFF

Q1 OFF

Q2 ON

*PDD = PROPAGATION DELAY DIFFERENCE

tPLH

MAX.

tPHL

MAX.

PDD*

MAX.

MAX.

DEAD TIME

NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM

DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.

LED Drive Circuit

Considerations for Ultra

High CMR Performance

Without a detector shield, the

dominant cause of optocoupler

CMR failure is capacitive coupling

from the input side of the optocoupler,

through the package, to

the detector IC as shown in

Figure 20. The HCPL-4506,

HCPL-0466 and HCNW4506

improve CMR performance by

using a detector IC with an optically

transparent Faraday shield,

which diverts the capacitively

coupled current away from the

sensitive IC circuitry. However,

this shield does not eliminate the

capacitive coupling between the

LED and the optocoupler output

pins and output ground as shown

in Figure 21. This capacitive

coupling causes perturbations in

the LED current during common

mode transients and becomes the

major source of CMR failures for

a shielded optocoupler. The main

design objective of a high CMR

LED drive circuit becomes keeping

the LED in the proper state

(on or off) during common mode

transients. For example, the

recommended application circuit

(Figure 19), can achieve 15 kV/ms

CMR while minimizing component

complexity. Note that a CMOS

gate is recommended in Figure 19

to keep the LED off when the gate

is in the high state.

Another cause of CMR failure for

a shielded optocoupler is direct

coupling to the optocoupler

output pins through CLEDO1 and

CLEDO2 in Figure 21. Many factors

influence the effect and magnitude

of the direct coupling including:

the use of an internal or

external output pull-up resistor,

the position of the LED current

setting resistor, the connection of

the unused input package pins,

and the value of the capacitor at

the optocoupler output (CL).

Techniques to keep the LED in

the proper state and minimize the

effect of the direct coupling are

discussed in the next two

sections.

CMR with the LED On

(CMRL)

A high CMR LED drive circuit

must keep the LED on during

common mode transients. This is

achieved by overdriving the LED

current beyond the input

threshold so that it is not pulled

below the threshold during a

transient. The recommended

minimum LED current of 10 mA

provides adequate margin over

the maximum ITH of 5.0 mA (see

Figure 5) to achieve 15 kV/ms

CMR. Capacitive coupling is

higher when the internal load

resistor is used (due to CLEDO2)

and an IF = 16 mA is required to

obtain 10 kV/ms CMR.

The placement of the LED current

setting resistor effects the ability of

the drive circuit to keep the LED on

during transients and interacts with

the direct coupling to the

optocoupler output. For example,

the LED resistor in Figure 22 is

connected to the anode. Figure 23

shows the AC equivalent circuit for

Figure 22 during common mode

transients. During a +dVcm/dt in

Figure 23, the current available at

the LED anode (Itotal) is limited by

the series resistor. The LED current

(IF) is reduced from its DC value by

an amount equal to the current that

flows through CLEDP and CLEDO1.

The situation is made worse

1-62

because the current through CLEDO1

has the effect of trying to pull the

output high (toward a CMR failure)

at the same time the LED current is

being reduced. For this reason, the

recommended LED drive circuit

(Figure 19) places the current setting

resistor in series with the LED

cathode. Figure 24 is the AC equivalent

circuit for Figure 19 during

common mode transients. In this

case, the LED current is not

reduced during a +dVcm/dt transient

because the current flowing

through the package capacitance is

supplied by the power supply.

During a -dVcm/dt transient, however,

the LED current is reduced by

the amount of current flowing

through CLEDN. But, better CMR

performance is achieved since the

current flowing in CLEDO1 during a

negative transient acts to keep the

output low.

Coupling to the LED and output

pins is also affected by the connection

of pins 1 and 4. If CMR is

limited by perturbations in the LED

on current, as it is for the recommended

drive circuit (Figure 19),

pins 1 and 4 should be connected to

the input circuit common. However,

if CMR performance is limited by

direct coupling to the output when

the LED is off, pins 1 and 4 should

be left unconnected.

CMR with the LED Off

(CMRH)

A high CMR LED drive circuit must

keep the LED off (VF £ VF(OFF))

during common mode transients.

For example, during a +dVcm/dt

transient in Figure 24, the current

flowing through CLEDN is supplied

by the parallel combination of the

LED and series resistor. As long as

the voltage developed across the

resistor is less than VF(OFF) the LED

will remain off and no common

mode failure will occur. Even if the

LED momentarily turns on, the 100

pF capacitor from pins 6-5 will

keep the output from dipping below

the threshold. The recommended

LED drive circuit (Figure 19) provides

about 10 V of margin between

the lowest optocoupler output

voltage and a 3 V IPM threshold

during a 15 kV/ms transient with

VCM = 1500 V. Additional margin

can be obtained by adding a diode

in parallel with the resistor, as

shown by the dashed line connection

in Figure 24, to clamp the

voltage across the LED below

VF(OFF).

Since the open collector drive circuit,

shown in Figure 25, cannot

keep the LED off during a +dVcm/

dt transient, it is not desirable for

applications requiring ultra high

CMRH performance. Figure 26 is

the AC equivalent circuit for Figure

25 during common mode

transients. Essentially all the

current flowing through CLEDN

during a +dVcm/dt transient must

be supplied by the LED. CMRH

failures can occur at dV/dt rates

where the current through the LED

and CLEDN exceeds the input

threshold. Figure 27 is an

alternative drive circuit which does

achieve ultra high CMR

performance by shunting the LED

in the off state.

IPM Dead Time and

Propagation Delay

Specifications

The HCPL-4506, HCPL-0466 and

HCNW4506 include a Propagation

Delay Difference specification

intended to help designers minimize

“dead time” in their power inverter

designs. Dead time is the time

period during which both the high

and low side power transistors (Q1

and Q2 in Figure 28) are off. Any

overlap in Q1 and Q2 conduction

will result in large currents flowing

through the power devices between

the high and low voltage motor rails.

To minimize dead time the designer

must consider the propagation

delay characteristics of the optocoupler

as well as the characteristics

of the IPM IGBT gate drive

circuit. Considering only the delay

characteristics of the optocoupler

(the characteristics of the IPM

IGBT gate drive circuit can be

analyzed in the same way) it is

important to know the minimum

and maximum turn-on (tPHL) and

turn-off (tPLH) propagation delay

specifications, preferably over the

desired operating temperature

range.

The limiting case of zero dead time

occurs when the input to Q1 turns

off at the same time that the input

to Q2 turns on. This case

determines the minimum delay

between LED1 turn-off and LED2

turn-on, which is related to the

worst case optocoupler propagation

delay waveforms, as shown in

Figure 29. A minimum dead time of

zero is achieved in Figure 29 when

the signal to turn on LED2 is

delayed by (tPLH max - tPHL min) from

the LED1 turn off. Note that the

propagation delays used to calculate

PDD are taken at equal temperatures

since the optocouplers under

consideration are typically mounted

in close proximity to each other.

(Specifically, tPLH max and tPHL min

in the previous equation are not the

same as the tPLH max and tPHL min,

over the full operating temperature

range, specified in the data sheet.)

This delay is the maximum value for

the propagation delay difference

specification which is specified at

450 ns for the HCPL-4506, HCPL-

0466 and HCNW4506 over an

operating temperature range of

-40°C to 100°C.

Delaying the LED signal by the

maximum propagation delay difference

ensures that the minimum

dead time is zero, but it does not

tell a designer what the maximum

dead time will be. The maximum

dead time occurs in the highly

unlikely case where one optocoupler

with the fastest tPLH and another

with the slowest tPHL are in the

same inverter leg. The maximum

dead time in this case becomes the

sum of the spread in the tPLH and

tPHL propagation delays as shown in

Figure 30. The maximum dead time

is also equivalent to the difference

between the maximum and minimum

propagation delay difference

specifications. The maximum dead

time (due to the optocouplers) for

the HCPL-4506, HCPL-0466 and

HCNW4506 is 600 ns (= 450 ns -

(-150 ns)) over an operating

temperature range of -40°C to

100°C.